The invention involves new microarchitecture apparatus and methods for superscalar microprocessors that support multi-instruction issue, decoupled dataflow scheduling, out-of-order execution, register renaming, multi-level speculative execution, and precise interrupts. These are the Distributed Instruction Queue (DIQ) and the Modified Reorder Buffer (MRB). The DIQ is a new distributed instruction shelving technique that is an alternative to the reservation station (RS) technique and offers a more efficient (improved performance/cost) implementation. The Modified Reorder Buffer (MRB) is an improved reorder buffer (RB) result shelving technique eliminates the slow and expensive prioritized associative lookup, shared global buses, and dummy br...
Modern superscalar processors implement precise interrupts by using the Reorder Buffer (ROB). In som...
An instruction set architecture (ISA) suitable for future microprocessor design constraints is propo...
A great deal of the current research into computer architecture is directed at Multiple Instruction ...
A distributed instruction queue (DIQ) in a superscalar microprocessor supports multi-instruction iss...
Abstract. Modern reorder buffers (ROBs) were conceived to improve processor performance by allowing ...
DS is a new microarchitecture that combines decoupled (DAE) and superscalar techniques to exploit in...
Superscalar processors can achieve increased performance by issuing instructions out-of-order from t...
The reorder buffer and register file of a modern superscalar processor are both critical components ...
High performance superscalar microarchitectures exploit instruction-level parallelism (ILP) to impro...
Modern superscalar processors use wide instruction issue widths and out-of-order execution in order ...
To exploit instruction level parallelism, it is important not only to execute multiple memory refere...
Modern superscalar processors implement precise interrupts by using the Reorder Buffer (ROB). In som...
Superscalar processing is the latest in a long series of innovations aimed at producing ever-faster ...
In out-of-order issue superscalar microprocessors, instructions must be buffered before they are iss...
[[abstract]]This paper introduces a novel superscalar micro-architecture, called IAS-S, and its rela...
Modern superscalar processors implement precise interrupts by using the Reorder Buffer (ROB). In som...
An instruction set architecture (ISA) suitable for future microprocessor design constraints is propo...
A great deal of the current research into computer architecture is directed at Multiple Instruction ...
A distributed instruction queue (DIQ) in a superscalar microprocessor supports multi-instruction iss...
Abstract. Modern reorder buffers (ROBs) were conceived to improve processor performance by allowing ...
DS is a new microarchitecture that combines decoupled (DAE) and superscalar techniques to exploit in...
Superscalar processors can achieve increased performance by issuing instructions out-of-order from t...
The reorder buffer and register file of a modern superscalar processor are both critical components ...
High performance superscalar microarchitectures exploit instruction-level parallelism (ILP) to impro...
Modern superscalar processors use wide instruction issue widths and out-of-order execution in order ...
To exploit instruction level parallelism, it is important not only to execute multiple memory refere...
Modern superscalar processors implement precise interrupts by using the Reorder Buffer (ROB). In som...
Superscalar processing is the latest in a long series of innovations aimed at producing ever-faster ...
In out-of-order issue superscalar microprocessors, instructions must be buffered before they are iss...
[[abstract]]This paper introduces a novel superscalar micro-architecture, called IAS-S, and its rela...
Modern superscalar processors implement precise interrupts by using the Reorder Buffer (ROB). In som...
An instruction set architecture (ISA) suitable for future microprocessor design constraints is propo...
A great deal of the current research into computer architecture is directed at Multiple Instruction ...