ARB: A hardware mechanism for dynamic reordering of memory references

To exploit instruction level parallelism, it is important not only to execute multiple memory references per cycle, but also to reorder memory references, especially to execute loads before stores that precede them in the sequential instruction stream. To guarantee correctness of execution in such situations, memory reference addresses have to be disambiguated. This paper presents a novel hardware mechanism, called an Address Reso-lution Buffer (ARB), for performing dynamic reordering of memory references. The ARB supports the follow-ing features: (i) dynamic memory disambiguation in a decentralized manner, (ii) multiple memory references per cycle, (iii) out-of-order execution of memory references, (iv) unresolved loads and stores, (v) speculative loads and stores, and (vi) memory renaming. The paper presents the results of a simulation study that we con-ducted to verify the efficacy of the ARB for a superscalar processor. The paper also shows the ARB’s applica-tion in a multiscalar processor. Instruction-level parallel (ILP) processors boost performance by forming an instruction execution schedule, either statically or dynamically, in which the instructions are executed in an order that is different from the order in which they occur in the (sequential) program. This is called instruction reordering. Because memory referencing instructions account for a large fraction of the instructions in most programs, the ability t