An Instruction Set and Microarchitecture for Instruction Level Distributed Processing

An instruction set architecture (ISA) suitable for future microprocessor design constraints is proposed. The 1SA has hierarchical register files with a small number of ac-cumulators at the top. The instruction stream is divided into chains of dependent instructions (strands) where in-tra-strand dependences are passed through the accumula-tor. The general-purpose register file is used for commu-nication between strands and for holding global values that have many consumers. A microarchitecture to support the proposed ISA is proposed and evaluated. The microarchitecture consists of multiple, distributed processing elements. Each PE contains an instruction issue FIFO, a local register (ac-cumulator) and local copy of register file. The overall simplicity, hierarchical value communication, and dis-tributed intplementation will provide a very high clock speed and a relatively short pipeline while maintaining a form of superscalar out-of-order execution. Detailed timing simulations using translated program traces show the proposed microarchitecture is tolerant of global wire latencies. Ignoring the significant clock fre-quency advantages, a microarchitecture that supports a 4-wide fetch~decode pipeline, 8 serial PEs, and a two-cycle inter-PE communication latency performs as well as a conventional 4-way out-of-order superscalar processor.