The scientific community has gratefully embraced floating-point arithmetic to escape the close attention for accuracy and precision required in fixed-point computational styles. Though its deficiencies are well known, the role of the floating-point system as standard has kept other number representation systems from coming into practice. The paper discusses the relation between fixed and floating-point numbers from a pragmatic point of view that allows to mix both systems to optimize FPGA-based hardware accelerators. The method is developed for the Mitrion "processor on demand" technology, where a computationally intensive algorithm is transformed into a dedicated. The large gap in cycle time between fixed and floating-point operations and ...
This paper describes the parameterisation, implementation and eval-uation of floating-point adders a...
Floating point numbers are used in many applications that would be well suited to a higher parallel...
This paper presents the sequential and pipelined designs of a double precision floating point divide...
The scientific community has gratefully embraced floating-point arithmetic to escape the close atten...
In recent years we have investigated the use of a logarithmic number representation as an alternativ...
Abstract—With the density of FPGAs steadily increasing, FPGAs have reached the point where they are ...
We present low cost FPGA floating-point arithmetic circuits for all the common operations, i.e. addi...
FPGAs are increasingly being used in the high performance and scientific computing community to impl...
Floating point arithmetic is a common requirement in signal processing, image processing and real ti...
This paper presents a single precision floating point unit de-sign for multiplication and addition/s...
Most scientific computations use double precision floating point numbers. Recently, posits as an add...
It has been shown that FPGAs could outperform high-end microprocessors on floating-point computation...
This paper describes the architecture and implementation, from both the standpoint of target applica...
This paper describes the parameterisation, implementation and evaluation of floating-point adders a...
Due to inherent limitations of the fixed-point representation, it is sometimes desirable to perform ...
This paper describes the parameterisation, implementation and eval-uation of floating-point adders a...
Floating point numbers are used in many applications that would be well suited to a higher parallel...
This paper presents the sequential and pipelined designs of a double precision floating point divide...
The scientific community has gratefully embraced floating-point arithmetic to escape the close atten...
In recent years we have investigated the use of a logarithmic number representation as an alternativ...
Abstract—With the density of FPGAs steadily increasing, FPGAs have reached the point where they are ...
We present low cost FPGA floating-point arithmetic circuits for all the common operations, i.e. addi...
FPGAs are increasingly being used in the high performance and scientific computing community to impl...
Floating point arithmetic is a common requirement in signal processing, image processing and real ti...
This paper presents a single precision floating point unit de-sign for multiplication and addition/s...
Most scientific computations use double precision floating point numbers. Recently, posits as an add...
It has been shown that FPGAs could outperform high-end microprocessors on floating-point computation...
This paper describes the architecture and implementation, from both the standpoint of target applica...
This paper describes the parameterisation, implementation and evaluation of floating-point adders a...
Due to inherent limitations of the fixed-point representation, it is sometimes desirable to perform ...
This paper describes the parameterisation, implementation and eval-uation of floating-point adders a...
Floating point numbers are used in many applications that would be well suited to a higher parallel...
This paper presents the sequential and pipelined designs of a double precision floating point divide...