Hybrida flyttalsenheter i FPGA:er

Floating point numbers are used in many applications that would be well suited to a higher parallelism than that offered in a CPU. In these cases, an FPGA, with its ability to handle multiple calculations simultaneously, could be the solution. Unfortunately, floating point operations which are implemented in an FPGA is often resource intensive, which means that many developers avoid floating point solutions in FPGAs or using FPGAs for floating point applications. Here the potential to get less expensive floating point operations by using ahigher radix for the floating point numbers and using and expand the existingDSP block in the FPGA is investigated. One of the goals is that the FPGAshould be usable for both the users that have floating point in their designsand those who do not. In order to motivate hard floating point blocks in theFPGA, these must not consume too much of the limited resources. This work shows that the floating point addition will become smaller withthe use of the higher radix, while the multiplication becomes smaller by usingthe hardware of the DSP block. When both operations are examined at the sametime, it turns out that it is possible to get a reduced area, compared toseparate floating point units, by utilizing both the DSP block and higherradix for the floating point numbers