Combined Altitude and Underground Real-Time SER Characterization of CMOS Technologies on the ASTEP-LSM Platform

International Conference on Integrated Circuit Design and Technology, Austin, TX, MAY 18-20, 2009International audienceThis work surveys our 2005-2009 experimental contributions to develop a combined altitude and underground test platform devoted to the soft-error rate (SER) characterization of deca-nanometer CMOS technologies. The platform currently involves two complementary sites to separate the component of the SER induced by the cosmic rays from that caused by on-chip radioactive impurities: the Altitude SEE Test European Platform (ASTEP) located at the altitude of 2252m on the Plateau de Bure (French south Alps) and the Underground Laboratory of Modane (LSM) in the Frejus tunnel under 1700m of rock (4800 meters water equivalent). These two sites have both dedicated instrumentations for neutron monitoring and circuit SER characterization. Long-duration real-time experimental measurements obtained using several gigabits of SRAMs manufactured in CMOS 130 nm and 65 nm technologies are reported and analyzed