Extension of Moore’s Law Via Strained Technologies- The Strategies and Challenges

For recent manufacturable CMOS technologies to extend the Moore’s law, the interest in the strain engineering has been speed-up in recent years as a need in further scaling of CMOS devices for high speed and low power applications. Among those reported strain schemes [1-10], process-induced stress technique [1,6,10], strained-SiGe channel devices [3, 8], substrate engineering, and hybrid substrate technology [9] have been attractive for high speed and low power logic CMOS technologies. As a consequence, strain-silicon technology has lasted for several generations beyond the 90nm generation node and it now comes to the cross-road of whether we want to use the planar CMOS structure at 20nm-16nm node. Strained technology seems to be one of the efficient approaches whatever the changes of device structure might be. Although some exciting strain schemes may achieve current enhancement that are expected, the reliability issues of strain CMOS devices need to be taken into consideration in the using of strained structures [11-12]. Also, with the further scaling of device dimensions, variability becomes increasingly important. More efforts on the study of strain-induced reliability, variability, device drain current enhancement etc., become more interested and raised more attention. In this talk, the strain-silicon technology since 90nm generation node will be first introduced. Then