Different methods to introduce strain in thin silicon device layers are presented. Uniaxial strain is introduced in CMOS devices by process-induced stressors allowing the local generation of tensile or compressive strain in the channel region of MOSFETs. Biaxial strain is introduced by growing of thin silicon layers on SiGe buffers and their transfer to oxidized silicon substrates. The latter forms strained silicon on insulator (SSOI) wafers characterized by tensile strain only. Future CMOS device technologies require the combination of the global strain of SSOI substrates with local stressors to increase the device performance
For recent manufacturable CMOS technologies to extend the Moore’s law, the interest in the strain en...
peer reviewedAs scaling of the critical transistor dimensions below 65 nm has been slowed down, the ...
Uniaxial strain on wafer-level was realised by mechanically bending and direct wafer bonding of Si w...
peer reviewedDifferent methods to introduce strain in thin silicon device layers are presented. Unia...
The stress sensitivity of SSOI substrate offers a unique material platform for strain manipulation. ...
Strain techniques, such as incorporating SiGe, should boost performance in future generations of CMO...
Strained silicon-on-insulator (SSOI) is an emerging material that combines the benefits of strained ...
International audienceWe report a novel approach for engineering tensely strained Si layers on a rel...
International audienceWe report a novel approach for engineering tensely strained Si layers on a rel...
We report the creation of strained silicon on silicon (SSOS) substrate technology. The method uses a...
Here, we demonstrate a new process to fabricate tensily strained Si On Insulator substrates (sSOI). ...
Strain techniques, such as incorporating SiGe, should boost performance in future generations of CMO...
In this study, material investigations of strained Si/SiGe platforms for MOSFET applications are pre...
[[abstract]]The tensile strained Si, based on the misfit between Si and SiGe gives higher speed and ...
peer reviewedSSOI substrates were successfully fabricated using He+ ion implantation and annealing t...
For recent manufacturable CMOS technologies to extend the Moore’s law, the interest in the strain en...
peer reviewedAs scaling of the critical transistor dimensions below 65 nm has been slowed down, the ...
Uniaxial strain on wafer-level was realised by mechanically bending and direct wafer bonding of Si w...
peer reviewedDifferent methods to introduce strain in thin silicon device layers are presented. Unia...
The stress sensitivity of SSOI substrate offers a unique material platform for strain manipulation. ...
Strain techniques, such as incorporating SiGe, should boost performance in future generations of CMO...
Strained silicon-on-insulator (SSOI) is an emerging material that combines the benefits of strained ...
International audienceWe report a novel approach for engineering tensely strained Si layers on a rel...
International audienceWe report a novel approach for engineering tensely strained Si layers on a rel...
We report the creation of strained silicon on silicon (SSOS) substrate technology. The method uses a...
Here, we demonstrate a new process to fabricate tensily strained Si On Insulator substrates (sSOI). ...
Strain techniques, such as incorporating SiGe, should boost performance in future generations of CMO...
In this study, material investigations of strained Si/SiGe platforms for MOSFET applications are pre...
[[abstract]]The tensile strained Si, based on the misfit between Si and SiGe gives higher speed and ...
peer reviewedSSOI substrates were successfully fabricated using He+ ion implantation and annealing t...
For recent manufacturable CMOS technologies to extend the Moore’s law, the interest in the strain en...
peer reviewedAs scaling of the critical transistor dimensions below 65 nm has been slowed down, the ...
Uniaxial strain on wafer-level was realised by mechanically bending and direct wafer bonding of Si w...