Trends in processor architecture and design suggest that static speculation will become a candidate for implementation on future high-performance processors. In this dissertation, we shall examine issues related to the implementation and exploitation of static speculation. There are four primary results: 1) Precise Exceptions: Prior work in static speculation has not examined the interaction between exception handling and speculative instructions in any great detail. We investigate this interaction, exhibiting certain problematic subtleties that arise, and show how they can be overcome. 2) Speculative Tagging: Earlier proposals for implementing speculative instructions tended to have several drawbacks, including restricted applica...
Trace-level speculative multithreaded processors exploit trace-level speculation by means of two thr...
Modern multiprocessors are complex systems that often require years to design and verify. A signific...
A superscalar processor supporting speculative ex-ecution requires an instruction fetch mechanism th...
This paper proposes a new compiler technique that enables speculative execution of alternative progr...
The available instruction level parallelism (ILP) is extremely limited within basic blocks of non-nu...
International audienceTo maximize performance, out-of-order execution processors sometimes issue ins...
Research on compiler techniques for thread-level loop speculation has so far remained on studying it...
Superscalar processors, which execute basic blocks sequentially, cannot use much instruction level p...
A simultaneous multithreaded (SMT) processor is able to issue and execute instructions from several ...
Thread-level speculative execution is a technique that makes it pos-sible for a wider range of singl...
The major specific contributions are: (1) We introduce a new compiler analysis to identify the memor...
While dynamic languages are now mainstream choices for application development, most popular dynamic...
Commodity microprocessors uniformly apply branch prediction and single path speculative execution to...
Effectively utilizing available parallelism is becoming harder and harder as systems evolve to many-...
Static timing analysis of embedded software is important for systems with hard real-time constraints...
Trace-level speculative multithreaded processors exploit trace-level speculation by means of two thr...
Modern multiprocessors are complex systems that often require years to design and verify. A signific...
A superscalar processor supporting speculative ex-ecution requires an instruction fetch mechanism th...
This paper proposes a new compiler technique that enables speculative execution of alternative progr...
The available instruction level parallelism (ILP) is extremely limited within basic blocks of non-nu...
International audienceTo maximize performance, out-of-order execution processors sometimes issue ins...
Research on compiler techniques for thread-level loop speculation has so far remained on studying it...
Superscalar processors, which execute basic blocks sequentially, cannot use much instruction level p...
A simultaneous multithreaded (SMT) processor is able to issue and execute instructions from several ...
Thread-level speculative execution is a technique that makes it pos-sible for a wider range of singl...
The major specific contributions are: (1) We introduce a new compiler analysis to identify the memor...
While dynamic languages are now mainstream choices for application development, most popular dynamic...
Commodity microprocessors uniformly apply branch prediction and single path speculative execution to...
Effectively utilizing available parallelism is becoming harder and harder as systems evolve to many-...
Static timing analysis of embedded software is important for systems with hard real-time constraints...
Trace-level speculative multithreaded processors exploit trace-level speculation by means of two thr...
Modern multiprocessors are complex systems that often require years to design and verify. A signific...
A superscalar processor supporting speculative ex-ecution requires an instruction fetch mechanism th...