Superscalar processors, which execute basic blocks sequentially, cannot use much instruction level parallelism. Speculative execution has been proposed to execute basic blocks in parallel. A pure software approach suffers from low performance, because exception-generating instructions cannot be executed speculatively. We propose delayed exceptions, a combination of hardware and compiler extensions that can provide high performance and correct exception handling in compiler-based speculative execution. Delayed exceptions exploit the fact that exceptions are rare. The compiler assumes the typical case (no exceptions), schedules the code accordingly, and inserts runtime checks and fix-up code that ensure correct execution when exceptions do ha...
Fast track is a software speculation system that enables unsafe optimization of sequential code. It ...
Instruction Level Parallelism (ILP) speedups of an order-of-magnitude or greater may be possible usi...
A superscalar processor supporting speculative ex-ecution requires an instruction fetch mechanism th...
Compiler-controlled speculative execution has been shown to be effective in increasing the available...
Trends in processor architecture and design suggest that static speculation will become a candidate...
The major specific contributions are: (1) We introduce a new compiler analysis to identify the memor...
The available instruction level parallelism (ILP) is extremely limited within basic blocks of non-nu...
With processor vendors pursuing multicore products, often at the expense of the complexity and aggre...
Although compiler optimization techniques are standard and successful in non-real-time systems, if n...
Out-of-order processors heavily rely on speculation to achieve high performance, allowing instructio...
Superscalar and superpipelining techniques increase the overlap between the instructions in a pipeli...
AbstractException handling enables programmers to specify the behavior of a program when an exceptio...
In complex System-on-a-Chip (SoC) designs, designers often need to add new features into an original...
The design of an exception handling mechanism for communicating sequential processes is presented. I...
Java exception checks are designed to ensure that any faulting instruction causing a hardware except...
Fast track is a software speculation system that enables unsafe optimization of sequential code. It ...
Instruction Level Parallelism (ILP) speedups of an order-of-magnitude or greater may be possible usi...
A superscalar processor supporting speculative ex-ecution requires an instruction fetch mechanism th...
Compiler-controlled speculative execution has been shown to be effective in increasing the available...
Trends in processor architecture and design suggest that static speculation will become a candidate...
The major specific contributions are: (1) We introduce a new compiler analysis to identify the memor...
The available instruction level parallelism (ILP) is extremely limited within basic blocks of non-nu...
With processor vendors pursuing multicore products, often at the expense of the complexity and aggre...
Although compiler optimization techniques are standard and successful in non-real-time systems, if n...
Out-of-order processors heavily rely on speculation to achieve high performance, allowing instructio...
Superscalar and superpipelining techniques increase the overlap between the instructions in a pipeli...
AbstractException handling enables programmers to specify the behavior of a program when an exceptio...
In complex System-on-a-Chip (SoC) designs, designers often need to add new features into an original...
The design of an exception handling mechanism for communicating sequential processes is presented. I...
Java exception checks are designed to ensure that any faulting instruction causing a hardware except...
Fast track is a software speculation system that enables unsafe optimization of sequential code. It ...
Instruction Level Parallelism (ILP) speedups of an order-of-magnitude or greater may be possible usi...
A superscalar processor supporting speculative ex-ecution requires an instruction fetch mechanism th...