We present an analytical technique that uses fault injection data for estimating the coverage of concurrent error detection mechanisms in microprocessors. A major problem in such estimations is that the coverage depends on the program executed by the microprocessor as well as the input sequence to the program. We propose a method that predicts the error coverage for a specified input sequence based on fault injection data obtained for another input sequence. Our results show that post-injection analysis is a promising approach for reducing the cost of coverage estimation
A general framework for the design and analysis of distributed fault-tolerant systems is proposed in...
International audienceThis paper presents two error models to evaluate safety of a software error de...
The negative impact of the aggressive scaling of technology nodes on the sensitivity of CMOS devices...
Abstract. The effects of variations in the workload input when estimating error detection coverage u...
This thesis addresses three important steps in the selection of error detection mechanisms for micro...
In this thesis we present two prediction techniques for estimating the error coverage of target prog...
Hardware errors are projected to increase in modern computer systems due to shrinking feature sizes ...
International audienceSimulation-based fault injection is commonly used to estimate system vulnerabi...
International audienceFault injection attacks are considered one of the major threats to cyber-physi...
The authors propose an approach for fault analysis and simulation of networks designed to have concu...
The evolution of high-performance and low-cost microprocessors has led to their almost pervasive usa...
Aspect‐oriented programming provides an interesting approach for implementing software‐based fault t...
Graphics Processing Units (GPUs) are popular for reliability-conscious uses in High Performance Comp...
This paper proposes a novel approach to modeling of gate level timing errors during high-level instr...
With continued CMOS scaling, future shipped hardware will be increasingly vulnerable to in-the-field...
A general framework for the design and analysis of distributed fault-tolerant systems is proposed in...
International audienceThis paper presents two error models to evaluate safety of a software error de...
The negative impact of the aggressive scaling of technology nodes on the sensitivity of CMOS devices...
Abstract. The effects of variations in the workload input when estimating error detection coverage u...
This thesis addresses three important steps in the selection of error detection mechanisms for micro...
In this thesis we present two prediction techniques for estimating the error coverage of target prog...
Hardware errors are projected to increase in modern computer systems due to shrinking feature sizes ...
International audienceSimulation-based fault injection is commonly used to estimate system vulnerabi...
International audienceFault injection attacks are considered one of the major threats to cyber-physi...
The authors propose an approach for fault analysis and simulation of networks designed to have concu...
The evolution of high-performance and low-cost microprocessors has led to their almost pervasive usa...
Aspect‐oriented programming provides an interesting approach for implementing software‐based fault t...
Graphics Processing Units (GPUs) are popular for reliability-conscious uses in High Performance Comp...
This paper proposes a novel approach to modeling of gate level timing errors during high-level instr...
With continued CMOS scaling, future shipped hardware will be increasingly vulnerable to in-the-field...
A general framework for the design and analysis of distributed fault-tolerant systems is proposed in...
International audienceThis paper presents two error models to evaluate safety of a software error de...
The negative impact of the aggressive scaling of technology nodes on the sensitivity of CMOS devices...