Execution efficiency of memory instructions remains critically important. To this end, a plethora of techniques aims to cancel load and store requests as soon as they are issued to the first-level cache. This paper unifies the diversity of approaches that cancel memory instructions early by contributing with a novel architectural scheme. Prior to that, we introduce the notion of silent loads to generalize the loads that can be satisfied by the already available values of the physical register file and contribute with a new architectural concept to cancel such loads early. We then show that our unified approach covers the techniques of cancelling (1) forwarded loads that obtain values through load-to-load and store-to-load forwarding, (2) sm...
The storage for speculative values in superscalar processors is one of the main sources of complexit...
The speed gap between processor and memory continues to limit performance. To address this problem, ...
Memory encryption has so far often had too much overhead to be practical. If it were possible to red...
Execution efficiency of memory instructions remains critically important. To this end, a plethora of...
This paper introduces the notion of silent loads to classify load accesses that can be satisfied by ...
As multicore architectures have hit the mainstream, one of the challenges for future multicore desig...
The considerable gap between processor and DRAM speed and the power losses in the cache hierarchy ca...
The evolution of computer systems to continuously improve execution efficiency has traditionally emb...
Some memory writes have the particular behaviour of not modifying memory since the value they write ...
To alleviate the memory wall problem, current architec-tural trends suggest implementing large instr...
This paper presents a novel compiler directed technique to reduce the register pressure and power of...
The speed gap between processor and memory continues to limit performance. To address this problem, ...
The storage for speculative values in superscalar processors is one of the main sources of complexit...
To alleviate the memory wall problem, current architectural trends suggest implementing large instru...
This paper exploits small-value locality to accelerate the execution of memory instructions. We find...
The storage for speculative values in superscalar processors is one of the main sources of complexit...
The speed gap between processor and memory continues to limit performance. To address this problem, ...
Memory encryption has so far often had too much overhead to be practical. If it were possible to red...
Execution efficiency of memory instructions remains critically important. To this end, a plethora of...
This paper introduces the notion of silent loads to classify load accesses that can be satisfied by ...
As multicore architectures have hit the mainstream, one of the challenges for future multicore desig...
The considerable gap between processor and DRAM speed and the power losses in the cache hierarchy ca...
The evolution of computer systems to continuously improve execution efficiency has traditionally emb...
Some memory writes have the particular behaviour of not modifying memory since the value they write ...
To alleviate the memory wall problem, current architec-tural trends suggest implementing large instr...
This paper presents a novel compiler directed technique to reduce the register pressure and power of...
The speed gap between processor and memory continues to limit performance. To address this problem, ...
The storage for speculative values in superscalar processors is one of the main sources of complexit...
To alleviate the memory wall problem, current architectural trends suggest implementing large instru...
This paper exploits small-value locality to accelerate the execution of memory instructions. We find...
The storage for speculative values in superscalar processors is one of the main sources of complexit...
The speed gap between processor and memory continues to limit performance. To address this problem, ...
Memory encryption has so far often had too much overhead to be practical. If it were possible to red...