Energy saving through a simple load control mechanism

To alleviate the memory wall problem, current architectural trends suggest implementing large instruction windows able to maintain a high number of in-flight instructions. How-ever, the benefits achieved by these recent proposals may be limited because more instructions are executed down the wrong path of a mispredicted branch. The larger num-ber of misspeculated instructions involves increasing the en-ergy consumed compared to traditional designs with smaller instruction windows. Our analysis shows that, for some SPEC2000 integer benchmarks, up to 2,5X wrong-path load instructions are executed when the instruction window of a 4-way superscalar processor is increased from 256 to 1024 entries. This paper describes a simple speculative control tech-nique to prevent wrong-path load instructions from being executed. Our technique extends the functionality of the load-store queue to block those load instructions that de-pend on a hard-to-predict conditional branch until it is re-solved. If the branch is actually mispredicted, unnecessary cache misses can be avoided, saving energy down the wrong path. Furthermore, instructions that depend on a blocked load are not issued because their source values are not avail-able, which also saves dynamic energy. Our results show that the proposed mechanism reduces, on average, up to 26 % misspeculated load instructions and 18 % wrong-path instructions without any performance loss