A Simple Speculative Load Control Mechanism for Energy Saving

To alleviate the memory wall problem, current architec-tural trends suggest implementing large instruction windows able to maintain a high number of in-flight instructions. However, the benefits achieved by these recent proposals may be limited because more instructions are executed down the wrong path of a mispredicted branch, likely polluting the processor caches. The larger number of misspeculated instructions involves increasing the energy consumed com-pared to traditional designs with smaller instruction win-dows. Our analysis shows that, for some SPEC2000 integer benchmarks, up to 2,5X wrong-path load instructions are ex-ecuted when the instruction window of a 4-way superscalar processor is increased from 256 to 1024 entries. This paper describes a simple speculative control tech-nique to prevent wrong-path load instructions from being ex-ecuted. Our technique extends the functionality of the load-store queue to block those load instructions that depend on a hard-to-predict conditional branch until it is resolved. If the branch is actually mispredicted, unnecessary cache misses can be avoided, saving energy down the wrong path. Fur-thermore, instructions that depend on a blocked load are not issued because their source values are not available, which also saves energy. Our results show that the proposed mech-anism reduces, on average, up to 26 % misspeculated load instructions and 18 % wrong-path instructions without any performance loss.