Schedulability analysis for hard real-time systems requires bounds on the execution times of its tasks. To obtain useful bounds in the presence of caches, cache analysis is mandatory. The subject-matter of this article is the static analysis of the tree-based PLRU cache replacement policy (pseudo least-recently used), for which the precision of analyses lags behind those of other policies. We introduce the term subtree distance, which is important for the update behavior of PLRU and closely linked to the peculiarity of PLRU that allows cache contents to be evicted in "logarithmic time". Based on an abstraction of subtree distance, we define a must-analysis that is more precise than prior ones by excluding spurious logarithmic-time evicti...
International audienceComputer system and network performance can be significantly improved by cachi...
Cache memories have been introduced to decrease the access time to the information due to the increa...
Caches are segments of memory that store requested information in a system subject to a set of decis...
International audienceFor applications in worst-case execution time analysis and in security, it is ...
International audienceModern processors use cache memory: a memory access that “hits” the cache retu...
Domino effects have been shown to hinder a tight prediction of worst case execution times (WCET) on ...
International audienceOn real-time systems running under timing constraints, scheduling can be perfo...
International audienceCache memories in modern embedded processors are known to improve average memo...
The quest for time-predictable systems has led to the exploration of new hardware architectures that...
Abstract Hard real-time systems must obey strict timing constraints. Therefore, one needs to derive ...
International audienceThe static analysis of cache accesses consists in correctly predicting which a...
This thesis describes a model used to analyze the replacement decisions made by LRU and OPT (Least-R...
International audienceComputer system and network performance can be significantly improved by cachi...
Recent studies have shown that cache partitioning is an efficient technique to improve throughput, f...
The full text of this article is not available on SOAR. WSU users can access the article via IEEE Xp...
International audienceComputer system and network performance can be significantly improved by cachi...
Cache memories have been introduced to decrease the access time to the information due to the increa...
Caches are segments of memory that store requested information in a system subject to a set of decis...
International audienceFor applications in worst-case execution time analysis and in security, it is ...
International audienceModern processors use cache memory: a memory access that “hits” the cache retu...
Domino effects have been shown to hinder a tight prediction of worst case execution times (WCET) on ...
International audienceOn real-time systems running under timing constraints, scheduling can be perfo...
International audienceCache memories in modern embedded processors are known to improve average memo...
The quest for time-predictable systems has led to the exploration of new hardware architectures that...
Abstract Hard real-time systems must obey strict timing constraints. Therefore, one needs to derive ...
International audienceThe static analysis of cache accesses consists in correctly predicting which a...
This thesis describes a model used to analyze the replacement decisions made by LRU and OPT (Least-R...
International audienceComputer system and network performance can be significantly improved by cachi...
Recent studies have shown that cache partitioning is an efficient technique to improve throughput, f...
The full text of this article is not available on SOAR. WSU users can access the article via IEEE Xp...
International audienceComputer system and network performance can be significantly improved by cachi...
Cache memories have been introduced to decrease the access time to the information due to the increa...
Caches are segments of memory that store requested information in a system subject to a set of decis...