Domino effects have been shown to hinder a tight prediction of worst case execution times (WCET) on real-time hardware. First investigated by Lundqvist and Stenström, domino effects caused by pipeline stalls were shows to exist in the PowerPC by Schneider. This paper extends the list of causes of domino effects by showing that the pseudo LRU (PLRU) cache replacement policy can cause unbounded effects on the WCET. PLRU is used in the PowerPC PPC755, which is widely used in embedded systems, and some x86 models
While hardware caches are generally effective at improving application performance, they greatly co...
When constructing real-time systems, safe and tight estimations of the worst case execution time (WC...
Previous timing analysis methods have assumed that the worst-case instruction execution time necessa...
Computing tight WCET bounds in the presence of timing anomalies - found in almost any modern hardwar...
Schedulability analysis for hard real-time systems requires bounds on the execution times of its tas...
© Elsevier. This manuscript version is made available under the CC-BY-NC-ND 4.0 license http://crea...
International audienceFine-grained disabling and reconfiguration of hardwareelements (functional uni...
Cache memories in modern embedded processors are known to improve average memory access performance....
International audienceOn real-time systems running under timing constraints, scheduling can be perfo...
This paper explores timing anomalies in WCET analysis.Timing anomalies add to the complexity of WCET...
Cache memories have been extensively used to bridge the gap between high speed processors and relati...
Cache memories have been introduced to decrease the access time to the information due to the increa...
Worst-case execution time (WCET) analysis of systems with data caches is one of the key challenges i...
While caches have become invaluable for higher-end architectures due to their ability to hide, in pa...
While caches have become invaluable for higher-end architectures due to their ability to hide, in pa...
While hardware caches are generally effective at improving application performance, they greatly co...
When constructing real-time systems, safe and tight estimations of the worst case execution time (WC...
Previous timing analysis methods have assumed that the worst-case instruction execution time necessa...
Computing tight WCET bounds in the presence of timing anomalies - found in almost any modern hardwar...
Schedulability analysis for hard real-time systems requires bounds on the execution times of its tas...
© Elsevier. This manuscript version is made available under the CC-BY-NC-ND 4.0 license http://crea...
International audienceFine-grained disabling and reconfiguration of hardwareelements (functional uni...
Cache memories in modern embedded processors are known to improve average memory access performance....
International audienceOn real-time systems running under timing constraints, scheduling can be perfo...
This paper explores timing anomalies in WCET analysis.Timing anomalies add to the complexity of WCET...
Cache memories have been extensively used to bridge the gap between high speed processors and relati...
Cache memories have been introduced to decrease the access time to the information due to the increa...
Worst-case execution time (WCET) analysis of systems with data caches is one of the key challenges i...
While caches have become invaluable for higher-end architectures due to their ability to hide, in pa...
While caches have become invaluable for higher-end architectures due to their ability to hide, in pa...
While hardware caches are generally effective at improving application performance, they greatly co...
When constructing real-time systems, safe and tight estimations of the worst case execution time (WC...
Previous timing analysis methods have assumed that the worst-case instruction execution time necessa...