A novel high performance and reliability p-type floating gate n-channel flash EEPROM

[[abstract]]In the design of either n-channel or p-channel flash memory, a conventional n-type poly-Si floating gate (Tam et al., 1988; Ohnakado et al., 1995; Hsu et al., 1992; Chung et al., 1997) is normally used. None has been reported using p-type as a floating gate in these cells. Recently, p-type polysilicon gate technology in a dual gate CMOS process with p+ polysilicon gate has matured (Kurio et al., 1993). On the other hand, multi-level memory cell technology for bit cost reduction has gained a lot of interest (Aritome et al., 1995; Kencke et al., 1996). One major requirement is that the threshold voltage distributions for various states must be separated to avoid read errors. However, widely spread distributions need higher programming voltages. In this paper, we propose for the first time use of p-type polysilicon as the floating gate in an n-channel flash memory in order to improve the cell performance and reliability. Results show that the flash cell with p-type floating gate has much better performance by comparison with conventional n-type floating-gate structures, such as faster programming/erase speed, larger operating window, better read-disturb and endurance characteristics. Successful application of this flash memory cell for multi-level operation is also demonstrated[[fileno]]2030131030010[[department]]電機工程學