[[abstract]]A DMA controller that operates in the cycle-stealing mode transfers data by `stealing' bus cycles from an executing program. This cycle stealing operation retards the progress of the executing program and extends its execution time. In this paper we first present a method that bounds the worst-case execution time of a program executing concurrently with a cycle-stealing DMA I/O operation in the simple case where the execution time of each machine instruction is fixed. We next extend this method to deal with the case of instruction-cache architectures. We demonstrate the effectiveness of our methods by the results of simulations of several programs.[[fileno]]2030235030010[[department]]資訊工程學
<p>In commercial-off-the-shelf (COTS) multi-core systems, a task running on one core can be delayed ...
Modern many-core programmable accelerators are often composed by several computing units grouped in ...
Abstract: Many recent dynamic voltage-scaling (DVS) algorithms use hardware events (such as cache mi...
A DMA controller that operates in cycle-stealing mode transfers data by "stealing" bus cyc...
[[abstract]]A DMA controller that operates in the cycle-stealing mode transfers data by stealing bus...
[[abstract]]This paper describes an efficient algorithm which gives a bound on the worst-case execut...
[[abstract]]This paper describes an efficient algorithm which gives a bound on the worst-case execut...
90 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1997.A cycle-stealing DMA I/O task ...
The use of caches poses a difficult tradeoff for architects of real-time systems. While caches provi...
As the first step toward real-time multi-core computing, this paper presents a novel approach to bou...
Part 2: Work in ProgressInternational audienceThis paper presents an approach to prevent memory atta...
Direct Memory Access (DMA) is frequently used to transfer data between the main memory of a host com...
Separation between processes on top of an operating system or between guests in a virtualized enviro...
RAMAPRASAD, HARINI Analytically Bounding Data Cache Behavior for Real-Time Sys-tems. (Under the dire...
Bounding the worst-case DRAM performance for a real-time application is a challenging problem that i...
<p>In commercial-off-the-shelf (COTS) multi-core systems, a task running on one core can be delayed ...
Modern many-core programmable accelerators are often composed by several computing units grouped in ...
Abstract: Many recent dynamic voltage-scaling (DVS) algorithms use hardware events (such as cache mi...
A DMA controller that operates in cycle-stealing mode transfers data by "stealing" bus cyc...
[[abstract]]A DMA controller that operates in the cycle-stealing mode transfers data by stealing bus...
[[abstract]]This paper describes an efficient algorithm which gives a bound on the worst-case execut...
[[abstract]]This paper describes an efficient algorithm which gives a bound on the worst-case execut...
90 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1997.A cycle-stealing DMA I/O task ...
The use of caches poses a difficult tradeoff for architects of real-time systems. While caches provi...
As the first step toward real-time multi-core computing, this paper presents a novel approach to bou...
Part 2: Work in ProgressInternational audienceThis paper presents an approach to prevent memory atta...
Direct Memory Access (DMA) is frequently used to transfer data between the main memory of a host com...
Separation between processes on top of an operating system or between guests in a virtualized enviro...
RAMAPRASAD, HARINI Analytically Bounding Data Cache Behavior for Real-Time Sys-tems. (Under the dire...
Bounding the worst-case DRAM performance for a real-time application is a challenging problem that i...
<p>In commercial-off-the-shelf (COTS) multi-core systems, a task running on one core can be delayed ...
Modern many-core programmable accelerators are often composed by several computing units grouped in ...
Abstract: Many recent dynamic voltage-scaling (DVS) algorithms use hardware events (such as cache mi...