PREDICTING THE WORST-CASE EXECUTION TIME OF THE CONCURRENT EXECUTION OF INSTRUCTIONS AND CYCLE-STEALING DMA I/O OPERATIONS

[[abstract]]This paper describes an efficient algorithm which gives a bound on the worst-case execution times of the concurrent execution of CPU instructions and cycle-stealing DMA I/O operations. Simulations of several programs were conducted to evaluate this algorithm. Compared with the traditional pessimistic approach, the bound on the worst-case execution time produced by the algorithm is significantly tighter. For a sample program that multiplies two matrices while the I/O bus is fully utilized, our algorithm achieves a 39% improvement in the accuracy of the prediction.[[fileno]]2030235010008[[department]]資訊工程學