Cache Coherence for Approximate Computing

Coherence induced cache misses are an important aspect limiting the scalability of shared memory parallel programs. Many coherence misses are avoidable, namely misses due to false sharing – when different threads write to different memory addresses that are contained within the same cache block causing unnecessary invalidations. Our work leverages the domain of approximate computing and the value similarity within store values present in multi-threaded error-tolerant applications. We introduce a novel cache coherence protocol for approximate computing which implements an approximate store instruction and coherence states to allow some incoherence within approximatable shared data to mitigate both coherence misses and coherence traffic within various sharing patterns. For applications within multi-threaded Phoenix and AxBench suites, we see dynamic energy improvements within the NoC and memory hierarchy up to 50.1% and speedup up to 37.3% with low output error for approximate applications that exhibit false sharing.M.A.S