: Virtual memory based cache coherence is a mechanism that relies only on hardware that already exists on the microprocessors of a shared memory multiprocessor system, yet dynamically detects and resolves potential cache inconsistencies using virtualmemory techniques. The key feature of the approach is that the virtual memory translation hardware on each processor is used to detect shared accesses that could lead to memory incoherencies, and VM page fault handlers execute the appropriate actions to maintain cache coherence. VM-based cache coherence basically trades off design simplicity against increased software overheads. The work presented in this paper evaluates this tradeoff. We show that VM-based cache coherence performs well for sci...
In a shared-memory multiprocessor with private caches, cached copies of a data item must be kept con...
An adaptive cache coherence mechanism exploits semantic information about the expected or observed a...
Emerging multiprocessor architectures such as chip multiprocessors, embedded architectures, and mas...
Cache coherence is one of the main challenges to tackle when designing a shared-memory multiprocesso...
Caches have the potential to provide multiprocessors with an automatic mechanism for reducing both n...
We argue that OS-provided data coherence on non-cache-coherent NUMA multiprocessors (machines with a...
Directory-based cache coherence protocol is accepted as the common technique in large scale shared m...
Thesis (Ph. D.)--University of Washington, 1987Shared-memory multiprocessors offer increased computa...
With the advancement of design and fabrication of high-performance integrated circuits technology, i...
This thesis presents a new cache coherence protocol for shared bus multicache systems, and addresses...
In large scale machines, thousands of processor cycles, in other words, missed opportunities to issu...
Due to VLSI lithography problems and the limitation of additional architectural enhancements uniproc...
Architects have adopted the shared memory model that implicitly manages cache coherence and cache ca...
Parallel applications exhibit a wide variety of memory reference patterns. Designing a memory archit...
We present design details and some initial performance results of a novel scalable shared memory mul...
In a shared-memory multiprocessor with private caches, cached copies of a data item must be kept con...
An adaptive cache coherence mechanism exploits semantic information about the expected or observed a...
Emerging multiprocessor architectures such as chip multiprocessors, embedded architectures, and mas...
Cache coherence is one of the main challenges to tackle when designing a shared-memory multiprocesso...
Caches have the potential to provide multiprocessors with an automatic mechanism for reducing both n...
We argue that OS-provided data coherence on non-cache-coherent NUMA multiprocessors (machines with a...
Directory-based cache coherence protocol is accepted as the common technique in large scale shared m...
Thesis (Ph. D.)--University of Washington, 1987Shared-memory multiprocessors offer increased computa...
With the advancement of design and fabrication of high-performance integrated circuits technology, i...
This thesis presents a new cache coherence protocol for shared bus multicache systems, and addresses...
In large scale machines, thousands of processor cycles, in other words, missed opportunities to issu...
Due to VLSI lithography problems and the limitation of additional architectural enhancements uniproc...
Architects have adopted the shared memory model that implicitly manages cache coherence and cache ca...
Parallel applications exhibit a wide variety of memory reference patterns. Designing a memory archit...
We present design details and some initial performance results of a novel scalable shared memory mul...
In a shared-memory multiprocessor with private caches, cached copies of a data item must be kept con...
An adaptive cache coherence mechanism exploits semantic information about the expected or observed a...
Emerging multiprocessor architectures such as chip multiprocessors, embedded architectures, and mas...