ISODATA SOPC-FPGA implementation of image segmentation using NIOS-II processor

This paper presents an FPGA image segmentation-binarization system based on iterative self organizing DATA (ISODATA) threshold using histogram analysis for embedded systems. The histogram module computes pixels levels statistics which are used by the ISODATA algorithm module to determine the segmentation threshold. In our case, this threshold binarizes a gray-scale image into two values 0 or 255. The prototype of the complete system uses an ALTERA CYCLONE-II DE2 kit with a lot of component and interfaces, such as the SD-CARD reader or a camera to read the image to be segmented, the FPGA which will implement the intellectual property (IP) core calculation with the NIOS processor, the VGA interface to view the results, and possibly of the ETHERNET interface for data transfer via internet. The use of FPGA contains the ISODATA, histogram, NIOS processor and others custom altera IPs hardware modules greatly improves processing speed and allows the binarization application to be embedded on a single chipbbn. For the project elaboration, we have used QUARTUS-II software for the hardware development part with VHDL description, SOPCbuilder or QSYS for the integration of NIOS-system, and NIOS-II-STBECLIPSE for the software program with eclipse c++ langage