Hardware Accelerator Design for Image Processing

[[abstract]]This paper proposed an image processing system based on hardware accelerator design method in FPGA chip. The architectures of the image system will be described. A hardware accelerator for scaling image is designed with Avalon-MM burst mode in System-on-a-Programmable-Chip (SOPC). There is a human-machine interface which display on the LCD Touch Panel Module (LTM) is designed in the image processing system. A user can choose a scaling factor by touching screen panel, and then LTM will display a 640 × 480 image on the LTM screen. Finally, the experimental result shows the comparison of the two design methods, and the hardware accelerator has better performance than Nios II processor.[[conferencetype]]國際[[conferencedate]]20120820~20120823[[booktype]]電子版[[booktype]]紙本[[iscallforpapers]]Y[[conferencelocation]]Bristol, U