Analysis of NOR Based Content Addressable Memory Cell Array

In VLSI the design metrics are area, power, delay, cost and speed which are very important for any design. These are the key parameters to control and manage. These parameters may or may not depend on each other. For example when delay is reduced the speed of the design increases and vice-versa but decrease in delay may not vary the power. So the power-delay product (PDP) is considered for any design. The project proposes method for reducing the delay which could give a good PDP factor. The project presents the Analysis of NOR based content addressable memory (CAM) Cells. As reducing the delay is becoming a basic need in data transfer of the networking this is more efficient than the existing conventional designs. To improve the functionality of the output in multiple matched cases a priority encoder is used. The proposed 16×8 CAM array design incorporates the enhanced array structures, decoder and priority encoder for better and reduced values of delays. These CAM arrays are designed using Cadence virtuoso tool with gpdk180 technology. The simulation carried out using Cadence Spectre tool. The proposed CAM array operates at faster than the existing CAM array. This method gave better power-delay product which is lesser than the existing method