Design and Characterization of New Content Addressable Memory Cells

This paper presents a new Content Addressable Memory (CAM) cell, designed in two variants (inverting and non-inverting), and optimized for power consumption. The cells are designed in 28 nm CMOS technology, using a fully-CMOS approach. If one of the bits in a word is not matching, the corresponding cell sends a "kill" signal to the cascaded cell to inhibit further switching. Thanks to this feature, the designed CAM array requires less than 0.7 fJ/bit per comparison. A prototype containing 2(17) words of 18 bits each has been fabricated and it has proven to be functional