Low-power dynamic CMOS circuits in high-performance memory arrays

Graduation date: 2009Dynamic CMOS circuits are commonly used in high-performance memory arrays to implement wide-NOR logic functions for their read and search operations. This is because dynamic circuits have significantly higher speed and lower area compared to static circuits for performing similar operations. Register File (RF) arrays are located at the top of the memory hierarchy for microprocessors providing the fastest data access. Reading data from RF arrays involves selection of data from memory cells based on input addresses, which is equivalent to the logical operation performed by wide-NOR gates. Content Addressable Memory (CAM) arrays are essential for high-performance comparison of an input data against a set of stored data. The hit or miss information from each memory cell is combined in wide-NOR gate like structures to generate the final miss or match information of the whole input search string.\ud The advantages of higher performance and lower area of dynamic circuits come at a cost of higher power and lower noise robustness compared to static circuits. With the advancement of process technology scaling, there is a trend of increase in leakage current which impacts both the power consumption and noise immunity. This dissertation presents design approaches to improve power consumption of high-performance RF and CAM arrays while maintaining their noise immunity.\ud The characteristics of an RF array depend on its bit-line organization. This dissertation investigates several bit-line arrangements with the same noise robustness and their impact on power and performance. The read evaluation circuits of traditional RF arrays are implemented with NMOS-device based domino gates where NMOS devices are used for evaluating dynamic nodes. An RF array with PMOS-device based domino gates is proposed, where the read evaluation is performed with PMOS devices instead of NMOS devices. \ud To improve power of RF based CAM arrays, an 11-transitor CAM cell is proposed. Its read/write operations are independent of the stored and/or search data and cell stability is independent of its read operation. A low-power Ternary Content Addressable Memory (TCAM) array using 16-transistor core memory cells is presented for network applications. It uses the same bit-lines for both read and search operations