High speed modified carry save adder using a structure of multiplexers

Adders are the heart of data path circuits for any processor in digitalcomputer and signal processing systems. Growth in technology keeps supporting efficient design of binary adders for high speed applications. Inthis paper, a fast and area-efficient modified carry save adder (CSA) is presented. A multiplexer based design of full adder is proposed to implement the structure of the CSA. The proposed design of full adder is employed indesigning all stages of traditional CSA. By modifying the design of full adderin CSA, the complexity and area of the design can be reduced, resulting inreduced delay time. The VHDL implementations of CSA adders including(the proposed version, traditional CSA, and modified CSAs presented inliterature) are simulated using Quartus II synthesis software tool with thealtera FPGA EP2C5T144C6 device (Cyclone II). Simulation results of 64-bitadder designs demonstrate the average improvement of 17.75%, 1.60%, and8.81% respectively for the worst case time, thermal power dissipation andnumber of FPGA logic elements