Design of High-Speed Hybrid Carry Select Adders using VHDL

Carry select adder (CSA) is a square-root time high-speed adder. CSA is one of the fastest adders used in many data processing systems to perform fast arithmetic operations. In this project we propose to design hybrid carry select adders with a focus on high speed. CSA is a compromise between the longer delay Ripple carry adder (RCA) and the shorter delay Carry look-ahead adder (CLA). Conventionally carry select adders are realize using the full adders and 2:1 multiplexers. On the other hand hybrid carry select adders involve a combination of carry select and carry look-ahead adders.In this work, we propose to design hybrid carry select adders involving carry select and carry look-ahead adders with and without ripple carry adder (RCA) using very high speed integrated circuits hardware description language (VHDL)