Designing and Performance Evaluation of Carry Select Adder

In electronics, adder is a digital circuit that performs addition of numbers. To perform fast arithmetic operations, carry select adder (CSA) is one of the fastest adder in processor architectures. This paper presents a modified carry select adder(CSA) that operates at low power and proves more area and delay efficient. Validation of the logic is done through extensive simulations for measuring the power and delay. Simple and efficient gate level modification is used in order to reduce the area, delay and power of CSA.The result analysis shows that the proposed structure(CSA CBL) is better than the conventional CSA and CSA with BEC