System-Level Design for Robustness

The increasing demand for compactness and speed of digital circuits and the necessity of integration of the digital backend electronics with radio frequency frontends, calls for exploiting deep submicron technologies in RF circuit design. However, scaling into the deep submicron regime, mainly in CMOS technologies, accentuates the effect of process spread and mismatch on the fabrication yield [10]. Furthermore, design for manufacturability requires all manufacturing and process variations to be considered in the design procedure. Statistical circuit-level methods based on modeling data provided by fabrication foundries, e.g. Monte Carlo, are extensively used to evaluate the effect of process spread and are utilized by simulation tools to design circuits with the desired performance over the specified range of process variation [8]. However, most of these statistical methods are based on random variation of design variables which need long simulation times for large-scale circuits, like a full receiver. Furthermore, as the size and complexity of designs is increased, less insight is obtained from these random statistical methods.