For multimedia applications, loop buffering is an efficient mechanism to reduce the power in the instruction memory of embedded processors. In particular, software controlled clustered loop buffers are very energy efficient. However code transformations needed in VLIW compilers to reach a higher ILP potentially may have a large negative influence on the energy consumed in the instruction memories (including the loop buffer). This paper will show that such code transformations can also have a positive impact on the instruction memory energy of processors, if the transformations are steered taking into account the presence of the software controlled clustered loop buffer. We will propose guidelines to steer the code transformations and show t...
International audienceUsual cache optimisation techniques for high performance computing are difficu...
Embedded systems require maximum performance from a processor within significant constraints in powe...
The rapidly increasing number of architectural changes in embedded processors puts compiler technolo...
For multimedia applications, loop buffering is an efficient mechanism to reduce the power in the ins...
For multimedia applications, loop buffering is an efficient mechanism to reduce the power in the ins...
For multimedia applications, loop buffering is an efficient mechanism to reduce the power in the ins...
Portable consumer electronics to play multimedia have to be high performant and flexible. Energy con...
\u3cp\u3eEnergy consumption in embedded systems is strongly dominated by instruction memory organiza...
Current loop buffer organizations for very large instruction word processors are essentially central...
Recent studies show that very long instruction word (VLIW) architectures, which inherently have wide...
Energy consumption is becoming an important issue on modern processors, especially on embedded syste...
textSoftware pipelining is a performance enhancing loop optimization technique widely used in optim...
This work aims to reduce the power consumed in the instruction memory of instruction set processors ...
Abstract—Current loop buffer organizations for very large instruction word processors are essentiall...
In this paper we propose a technique that uses an ad-ditional mini cache located between the I-Cache...
International audienceUsual cache optimisation techniques for high performance computing are difficu...
Embedded systems require maximum performance from a processor within significant constraints in powe...
The rapidly increasing number of architectural changes in embedded processors puts compiler technolo...
For multimedia applications, loop buffering is an efficient mechanism to reduce the power in the ins...
For multimedia applications, loop buffering is an efficient mechanism to reduce the power in the ins...
For multimedia applications, loop buffering is an efficient mechanism to reduce the power in the ins...
Portable consumer electronics to play multimedia have to be high performant and flexible. Energy con...
\u3cp\u3eEnergy consumption in embedded systems is strongly dominated by instruction memory organiza...
Current loop buffer organizations for very large instruction word processors are essentially central...
Recent studies show that very long instruction word (VLIW) architectures, which inherently have wide...
Energy consumption is becoming an important issue on modern processors, especially on embedded syste...
textSoftware pipelining is a performance enhancing loop optimization technique widely used in optim...
This work aims to reduce the power consumed in the instruction memory of instruction set processors ...
Abstract—Current loop buffer organizations for very large instruction word processors are essentiall...
In this paper we propose a technique that uses an ad-ditional mini cache located between the I-Cache...
International audienceUsual cache optimisation techniques for high performance computing are difficu...
Embedded systems require maximum performance from a processor within significant constraints in powe...
The rapidly increasing number of architectural changes in embedded processors puts compiler technolo...