Instruction transfer and storage exploration for low energy embedded VLIWs

Portable consumer electronics to play multimedia have to be high performant and flexible. Energy consumption has to be kept as low as possible to ensure a long battery lifetime. To be flexible, these systems often contain an instruction set processor. Very Long Instruction Word (VLIW) processors have proven to provide sufficient performance, with reasonably low energy consumption for multimedia applications. However energy analysis indicates that within these processors, a significant amount of energy is consumed in instruction memories. This dissertation proposes ITSE (Instruction Transfer and Storage Exploration), a methodology for low energy design and use of instruction memories based on a loop buffer architecture. A loop buffer is a very small memory, close to the processor core that is used to execute the most important loops of the program running on the processor. Since it is a small memory, it will be energy efficient. Different opportunities exist to reduce the instruction memory energy using this loop buffer. These opportunities are implemented in the different steps of the methodology and these steps are described in this dissertation. As a first step, we propose an effective method to manage a software controlled loop buffer using a pre-compiler. By carefully deciding what loops have to be executed from the loop buffer and when to copy these loops into the loop buffer memory, we are able to reduce the instruction memory energy significantly. The impact on the instruction memory energy of source code transformations typically found in VLIW compilers is analyzed. Two types of transformations exist, namely transformations that reduce the number of operations and transformations that increase the instruction level parallelism. For both types of transformations, guidelines are proposed on how to apply the transformations, taking into account the instruction memory energy aspects. We show that the instruction memory optimizations do not conflict with the data memory optimizations. Results are presented for the different steps of the methodology on various benchmark applications, and the complete methodology is demonstrated on a real-life example