In the high-level synthesis of ASICs or in the code generation for ASIPs, the presence of conditionals in the behavioral description represents an obstacle to exploit parallelism. Most existing methods use greedy choices in such a way that the search space is limited by the applied heuristics. For example, they might miss opportunities to optimize across basic block boundaries when treating conditional execution. We propose a constructive method which allows generalized code motions. Scheduling and code motion are encoded in the form of a unified resource-constrained optimization problem. In our approach many alternative solutions are constructed and explored by a search algorithm, while optimal solutions are kept in the search space. Our m...
Emerging design problems are prompting the use of code motion and speculation in high–level synthesi...
International audienceAs hardware designs get increasingly complex and time-to-market constraints ge...
In code generation, instruction selection chooses processor instructions to implement a program unde...
In the high-level synthesis of ASICs or in the code generation for ASIPs, the presence of conditiona...
In this paper we address a resource-constrained optimization problem for behavioral descriptions con...
In this paper we address a resource--constrained optimization problem for behavioral descriptions co...
In this paper we address a resource–constrained optimization problem for behavioral descriptions con...
Emerging design problems are prompting the use of code motion and speculative execution in high-leve...
A new Global Resource-constrained Percolation (GRiP) scheduling technique is presented for exploitin...
Code motion is well-known as a powerful technique for the optimization of sequential programs. It im...
Programs that are not loop intensive and which have small basic blocks present a challenge to archit...
The quality of high-level synthesis results for designs with complex and nested conditionals and l...
An instruction scheduler utilizes code reordering techniques for generating schedules in which instr...
We present a technique for task response time improvement based on the concept of code motion from t...
International audienceThis paper presents a scheduling algorithm that improves on other approaches w...
Emerging design problems are prompting the use of code motion and speculation in high–level synthesi...
International audienceAs hardware designs get increasingly complex and time-to-market constraints ge...
In code generation, instruction selection chooses processor instructions to implement a program unde...
In the high-level synthesis of ASICs or in the code generation for ASIPs, the presence of conditiona...
In this paper we address a resource-constrained optimization problem for behavioral descriptions con...
In this paper we address a resource--constrained optimization problem for behavioral descriptions co...
In this paper we address a resource–constrained optimization problem for behavioral descriptions con...
Emerging design problems are prompting the use of code motion and speculative execution in high-leve...
A new Global Resource-constrained Percolation (GRiP) scheduling technique is presented for exploitin...
Code motion is well-known as a powerful technique for the optimization of sequential programs. It im...
Programs that are not loop intensive and which have small basic blocks present a challenge to archit...
The quality of high-level synthesis results for designs with complex and nested conditionals and l...
An instruction scheduler utilizes code reordering techniques for generating schedules in which instr...
We present a technique for task response time improvement based on the concept of code motion from t...
International audienceThis paper presents a scheduling algorithm that improves on other approaches w...
Emerging design problems are prompting the use of code motion and speculation in high–level synthesi...
International audienceAs hardware designs get increasingly complex and time-to-market constraints ge...
In code generation, instruction selection chooses processor instructions to implement a program unde...