An instruction scheduler utilizes code reordering techniques for generating schedules in which instructions can be issued without delays. In order to perform code reordering across branches, code motion is performed that hoists some instructions above branches and sinks others below branches. Following code reordering, compensation code must be introduced in order to preserve program semantics. In this paper we demonstrate that several important code optimizations can be performed as a side effect of generating compensation code. These optimizations include partial redundancy elimination, partial dead code elimination, elimination of redundant loads, and elimination of dead stores. We demonstrate how existing data flow frameworks for these ...
Poor instruction cache locality can degrade performance on modern architectures. For example, our si...
Whether code is created by a programmer or generated by a compiler, its construction is traditionall...
Two of the most important phases of code generation for instruction level parallel processors are re...
. Code optimizations and restructuring transformations are typically applied before scheduling to im...
Value-driven redundancy elimination is a combination of value numbering and code motion. Value numbe...
For dynamic optimization systems, success is limited by two difficult problems arising from instruct...
Instruction scheduling algorithms are used in compilers to reduce run-time delays for the compiled c...
This work was also published as a Rice University thesis/dissertation: http://hdl.handle.net/1911/16...
Effective global instruction scheduling techniques have become an important component in modern comp...
The AVIV retargetable code generator produces optimized machine code for target processors with diff...
Instruction scheduling and Software pipelining are important compilation techniques which reorder in...
[[abstract]]A pipelined processor increases its performance by partitioning an instruction into seve...
In code generation, instruction selection chooses processor instructions to implement a program unde...
Instruction scheduling is a code reordering transformation that attempts to hide latencies present i...
We advocate using performance bounds to guide code optimizations. Accurate performance bounds establ...
Poor instruction cache locality can degrade performance on modern architectures. For example, our si...
Whether code is created by a programmer or generated by a compiler, its construction is traditionall...
Two of the most important phases of code generation for instruction level parallel processors are re...
. Code optimizations and restructuring transformations are typically applied before scheduling to im...
Value-driven redundancy elimination is a combination of value numbering and code motion. Value numbe...
For dynamic optimization systems, success is limited by two difficult problems arising from instruct...
Instruction scheduling algorithms are used in compilers to reduce run-time delays for the compiled c...
This work was also published as a Rice University thesis/dissertation: http://hdl.handle.net/1911/16...
Effective global instruction scheduling techniques have become an important component in modern comp...
The AVIV retargetable code generator produces optimized machine code for target processors with diff...
Instruction scheduling and Software pipelining are important compilation techniques which reorder in...
[[abstract]]A pipelined processor increases its performance by partitioning an instruction into seve...
In code generation, instruction selection chooses processor instructions to implement a program unde...
Instruction scheduling is a code reordering transformation that attempts to hide latencies present i...
We advocate using performance bounds to guide code optimizations. Accurate performance bounds establ...
Poor instruction cache locality can degrade performance on modern architectures. For example, our si...
Whether code is created by a programmer or generated by a compiler, its construction is traditionall...
Two of the most important phases of code generation for instruction level parallel processors are re...