The most important processor performance bottleneck is the ever-increasing gap between the memory and the processor speeds. To close this gap, current microprocessors employ cache hierarchies. Caches hide the memory latency by keeping the most frequently and recently used data closer to the processor. However, caches are limited in size and must be managed intelligently. In this research, we introduce a notion of Reference Value Caches (RVC). We explored the potential by tracking the blocks that contains reference values more than given threshold. Our findings show that frequent values embrace at least %50 of the loads. We also show that with only using four reference values for our implementation, we achieved speedups up to 10%
Distinguishing transient blocks from frequently used blocks enables servicing references to transien...
Application performance on modern microprocessors depends heavily on performance related characteris...
Value specialization is a technique which can improve a program’s performance when its code frequent...
This paper introduces the abstract concept of value-aware caches, which exploit value locality rathe...
Address correlation is a technique that links the addresses that reference the same data values. Usi...
To maximize the benefit and minimize the overhead of software-based latency tolerance techniques, we...
Applications often under-utilize cache space and there are no software locality optimization techniq...
While caches have become invaluable for higher-end architectures due to their ability to hide, in pa...
We introduce a method for improving the cache performance of irregular computations in which data ar...
On-chip cache memories are instrumental in tackling several performance and energy issues facing con...
Memory (cache, DRAM, and disk) is in charge of providing data and instructions to a computer\u27s pr...
Benefits of advances in processor technology have long been held hostage to the widening processor-m...
Minimizing power, increasing performance, and delivering effective memory bandwidth are today's prim...
As the processor-memory performance gap continues to grow, so does the need for effective tools and ...
Highly aggressive multi-issue processor designs of the past few years and projections for the next d...
Distinguishing transient blocks from frequently used blocks enables servicing references to transien...
Application performance on modern microprocessors depends heavily on performance related characteris...
Value specialization is a technique which can improve a program’s performance when its code frequent...
This paper introduces the abstract concept of value-aware caches, which exploit value locality rathe...
Address correlation is a technique that links the addresses that reference the same data values. Usi...
To maximize the benefit and minimize the overhead of software-based latency tolerance techniques, we...
Applications often under-utilize cache space and there are no software locality optimization techniq...
While caches have become invaluable for higher-end architectures due to their ability to hide, in pa...
We introduce a method for improving the cache performance of irregular computations in which data ar...
On-chip cache memories are instrumental in tackling several performance and energy issues facing con...
Memory (cache, DRAM, and disk) is in charge of providing data and instructions to a computer\u27s pr...
Benefits of advances in processor technology have long been held hostage to the widening processor-m...
Minimizing power, increasing performance, and delivering effective memory bandwidth are today's prim...
As the processor-memory performance gap continues to grow, so does the need for effective tools and ...
Highly aggressive multi-issue processor designs of the past few years and projections for the next d...
Distinguishing transient blocks from frequently used blocks enables servicing references to transien...
Application performance on modern microprocessors depends heavily on performance related characteris...
Value specialization is a technique which can improve a program’s performance when its code frequent...