Add to ORKGWe formulate statistical static timing analysis (SSTA) as a mixed-integer program and as a geometric program, utilizing histogram approximations of the random variables involved. The geometric-programming approach scales linearly with the number of gates and quadratically with the number of bins in the histogram. This translates, for example, to solving the SSTA for a circuit of 400 gates with 30 bins per each histogram approximation of a random variable in 440 seconds.Comment: 23 pages, 7 figure
A vast literature has been published on Statistical Static Timing Analysis (SSTA), its motivations, ...
2011-10-03Static timing analysis (STA) is a key tool used for the design, optimization, and final si...
Abstract—As technology scales into the sub-90nm domain, manufacturing variations become an increasin...
The effect of process variation is getting worse with every technology generation. With variability ...
As CMOS technology scales down, process variation introduces significant uncertainty in power and pe...
textTechnology scaling in the nanometer era comes with a significant amount of process variation, le...
The move to deep submicron processes has brought about new problems that designers must contend with...
Timing analysis is a key step in the digital design process. By modeling device delay variations sta...
As CMOS technology continues to scale down, process variation introduces significant uncertainty in ...
An efficient and accurate statistical static timing analysis (SSTA) algorithm is reported in this wo...
In the recent nanotechnology, the variation in the gate propagation delay is the big concern. This p...
Abstract Statistical static timing analysis (SSTA) has emerged as an essential tool for nanoscale de...
Statistical static timing analysis (SSTA) involves computation of maximum (max) and minimum (min) of...
This paper proposed the impact of variations on delay in CMOS technology of 32 nm. The magnitude of ...
Abstract—The most challenging problem in the current block-based statistical static timing analysis ...
A vast literature has been published on Statistical Static Timing Analysis (SSTA), its motivations, ...
2011-10-03Static timing analysis (STA) is a key tool used for the design, optimization, and final si...
Abstract—As technology scales into the sub-90nm domain, manufacturing variations become an increasin...
The effect of process variation is getting worse with every technology generation. With variability ...
As CMOS technology scales down, process variation introduces significant uncertainty in power and pe...
textTechnology scaling in the nanometer era comes with a significant amount of process variation, le...
The move to deep submicron processes has brought about new problems that designers must contend with...
Timing analysis is a key step in the digital design process. By modeling device delay variations sta...
As CMOS technology continues to scale down, process variation introduces significant uncertainty in ...
An efficient and accurate statistical static timing analysis (SSTA) algorithm is reported in this wo...
In the recent nanotechnology, the variation in the gate propagation delay is the big concern. This p...
Abstract Statistical static timing analysis (SSTA) has emerged as an essential tool for nanoscale de...
Statistical static timing analysis (SSTA) involves computation of maximum (max) and minimum (min) of...
This paper proposed the impact of variations on delay in CMOS technology of 32 nm. The magnitude of ...
Abstract—The most challenging problem in the current block-based statistical static timing analysis ...
A vast literature has been published on Statistical Static Timing Analysis (SSTA), its motivations, ...
2011-10-03Static timing analysis (STA) is a key tool used for the design, optimization, and final si...
Abstract—As technology scales into the sub-90nm domain, manufacturing variations become an increasin...