Abstract—As technology scales into the sub-90nm domain, manufacturing variations become an increasingly significant portion of circuit delay. As a result, delays must be modeled as statistical distributions during both analysis and optimization. This paper uses incremental, parametric statistical static timing analysis (SSTA) to perform gate sizing with a required yield target. Both correlated and uncorrelated process parameters are considered by using a first-order linear delay model with fitted process sensitivities. The fitted sensitivities are verified to be accurate with circuit simulations. Statistical information in the form of criticality probabilities are used to actively guide the optimization process which reduces run-time and im...
Abstract—This paper presents novel techniques for timing yield optimization and for yield estimation...
In the recent nanotechnology, the variation in the gate propagation delay is the big concern. This p...
MasterThe variations of process parameters have increased due to the continued scaling down of semic...
Abstract—In this paper, we propose a statistical gate sizing ap-proach to maximize the timing yield ...
Abstract In this paper, we approach the gate sizing problem in VLSI circuits in the context of incr...
The effect of process variation is getting worse with every technology generation. With variability ...
Variability of process parameters makes prediction of digital circuit timing characteristics an impo...
Abstract — Process variations cause design performance to become unpredictable in deep sub-micron te...
Gate sizing is one of the most flexible and powerful methods available for the timing and power opti...
In this paper we have applied statistical sizing in an industrial setting. Efficient implementation ...
The move to deep submicron processes has brought about new problems that designers must contend with...
DoctorAggressive technology scaling in feature size has propelled designers to integrate millions of...
Aggressive device scaling has made it imperative to account for process variations in the design flo...
2011-10-03Static timing analysis (STA) is a key tool used for the design, optimization, and final si...
Variability of circuit performance is becoming a very im-portant issue for ultra-deep sub-micron tec...
Abstract—This paper presents novel techniques for timing yield optimization and for yield estimation...
In the recent nanotechnology, the variation in the gate propagation delay is the big concern. This p...
MasterThe variations of process parameters have increased due to the continued scaling down of semic...
Abstract—In this paper, we propose a statistical gate sizing ap-proach to maximize the timing yield ...
Abstract In this paper, we approach the gate sizing problem in VLSI circuits in the context of incr...
The effect of process variation is getting worse with every technology generation. With variability ...
Variability of process parameters makes prediction of digital circuit timing characteristics an impo...
Abstract — Process variations cause design performance to become unpredictable in deep sub-micron te...
Gate sizing is one of the most flexible and powerful methods available for the timing and power opti...
In this paper we have applied statistical sizing in an industrial setting. Efficient implementation ...
The move to deep submicron processes has brought about new problems that designers must contend with...
DoctorAggressive technology scaling in feature size has propelled designers to integrate millions of...
Aggressive device scaling has made it imperative to account for process variations in the design flo...
2011-10-03Static timing analysis (STA) is a key tool used for the design, optimization, and final si...
Variability of circuit performance is becoming a very im-portant issue for ultra-deep sub-micron tec...
Abstract—This paper presents novel techniques for timing yield optimization and for yield estimation...
In the recent nanotechnology, the variation in the gate propagation delay is the big concern. This p...
MasterThe variations of process parameters have increased due to the continued scaling down of semic...