Statistical static timing analysis and circuit optimization.

The effect of process variation is getting worse with every technology generation. With variability in device features, circuit delay is no longer a deterministic quantity but a random variable during the design phase. Similarly, other parameters that have been traditionally considered as deterministic, such as slack and clock skew, also become random variables. Statistical Static Timing Analysis (SSTA) aims to attain the statistical distribution of these random variables over the sample space of manufactured dies. Such an analysis is useful to predict the timing yield distribution for the dies. A statistical timing engine is also useful in performing circuit optimization in order to increase robustness and to increase the expected profit by optimizing the yield curve. In our research, we provide efficient and accurate algorithmic solutions to the problem of SSTA. Both path-based and block-based approaches are considered in our analysis. In the path-based approach, we perform an accurate analysis considering slope variation, loading variation and variation due to spatial correlations. In the block-based approach, we first consider the problem of reconvergence and propose bounds on the circuit delay with linear run-time. We then propose a novel model for handling spatial correlations, and extend our bound-based approach to handle these correlations. Also, our delay model handles both inter- and intra-die variations including random and spatial components.PhDApplied SciencesElectrical engineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/125005/2/3186560.pd