In this paper, a novel architecture for self-timed analog-to-digital conversion is presented and designed using the NULL Convention Logic (NCL) paradigm. This analog-to-digital converter (ADC) employs successive approximation and a one-hot encoded masking technique to digitize analog signals. The architecture scales readily to any given resolution by utilizing the one-hot encoded scheme to permit identical logical components for each bit of resolution. The four-bit configuration of the proposed design has been implemented and assessed via simulation in 0.18-μm CMOS technology. Furthermore, the ADC may be interfaced with either synchronous or four-phase asynchronous digital systems. © World Scientific Publishing Company
Self-timed logic design methods are developed using Threshold Combinational Reduction (TCR) within t...
According to the advantages of the digital signal processing, we turn us towards the numerical field...
This paper presents an analog-to-digital converter (ADC), using pipelined successive approximation r...
In this paper, a novel architecture for self-timed analog-to-digital conversion is presented and des...
In this paper, a novel architecture for self-timed analog-to-digital conversion is presented and des...
In this paper, a novel architecture for self-timed analog-to-digital conversion is presented, design...
International audienceWe present a new class of Asynchronous Analog to Digital Converters (A-ADCs), ...
A well known problem of time-interleaved analogto-digital converters is the matching between the ind...
This work is a contribution to a drastic change in standard signal processing chains. The main objec...
This work investigates new approaches to analog-to-digital conversion that are suited for end-of-the...
International audienceWe present a new class of Analog-to-Digital Converters (ADCs), based on an irr...
Self-timed multipliers, designed using the delay-insensitive null convention logic (NCL) paradigm, w...
Analog-to-digital converters (ADCs) are key design blocks and are currently adopted in many applicat...
We present a new class of asynchronous analog to digital converters (A-ADCs), based on an level-cros...
This thesis discusses the d es ign and verification of a high-resolution self-timed incremental ?? A...
Self-timed logic design methods are developed using Threshold Combinational Reduction (TCR) within t...
According to the advantages of the digital signal processing, we turn us towards the numerical field...
This paper presents an analog-to-digital converter (ADC), using pipelined successive approximation r...
In this paper, a novel architecture for self-timed analog-to-digital conversion is presented and des...
In this paper, a novel architecture for self-timed analog-to-digital conversion is presented and des...
In this paper, a novel architecture for self-timed analog-to-digital conversion is presented, design...
International audienceWe present a new class of Asynchronous Analog to Digital Converters (A-ADCs), ...
A well known problem of time-interleaved analogto-digital converters is the matching between the ind...
This work is a contribution to a drastic change in standard signal processing chains. The main objec...
This work investigates new approaches to analog-to-digital conversion that are suited for end-of-the...
International audienceWe present a new class of Analog-to-Digital Converters (ADCs), based on an irr...
Self-timed multipliers, designed using the delay-insensitive null convention logic (NCL) paradigm, w...
Analog-to-digital converters (ADCs) are key design blocks and are currently adopted in many applicat...
We present a new class of asynchronous analog to digital converters (A-ADCs), based on an level-cros...
This thesis discusses the d es ign and verification of a high-resolution self-timed incremental ?? A...
Self-timed logic design methods are developed using Threshold Combinational Reduction (TCR) within t...
According to the advantages of the digital signal processing, we turn us towards the numerical field...
This paper presents an analog-to-digital converter (ADC), using pipelined successive approximation r...