Asynchronous level crossing analog to digital converters

We present a new class of asynchronous analog to digital converters (A-ADCs), based on an level-crossing sampling scheme of the analog signal, and an asynchronous design. Because these ADCs are not conventional, a design methodology is also presented, it takes place at a system level, then a transistor level. Its purpose is to determine the characteristics of an A-ADC given the required effective number of bits and the properties of the analog signal to convert, such as to minimize the complexity, the activity, and the power consumption. A prototype has been designed for speech applications, using the 0.18 μm CMOS technology from STMicroelectronics, and a voltage mode approach for the analog parts of the converter. Electrical simulations prove that the Figure of Merit (FoM) of this converter is increased by more than one order of magnitude compared to synchronous Nyquist ADCs. Moreover, behavioural simulations prove that the activity of the A-ADC is reduced by two orders of magnitude compared to its synchronous counterpart