Exploiting ultra-fine grain parallelism for machines with parallel pipelined datapaths

This report examines ultra-fine grain machine parallelism determined by various hardware styles and constraints. Two major components are incorporated in our system: (1) A generalized parameterized architecture model which characterizes different design styles and constraints based on parallel pipelined machines. (2) A retargetable compiler which maps instruction parallelism to ultra-fine grain machine parallelism for target architectures. Basically the generalized parameterized model is used to specify different target machines, and the retargetable compiler compiles and schedules applications, codes written in high-level language, into control codes for given target machines. The resulting control codes are run through a simulator, after which dynamic statistics of the execution are recorded and the ultra-fine grain parallelism of target machines is assessed. A set of studies has been conducted to demonstrate how ultra-fine grain machine parallelism is affected by various hardware parameters and how performance is affected by both instruction parallelism and machine parallelism