Prototyping Of Efficient Hardware Algorithms For Data Compression In Future Communication Systems

Due to high bandwidth requirements up to 2 Mbits/sec in third generation mobile communication systems, efficient data compression approaches are necessary to reduce communication and storage costs. Recent VLSI technologies status promises complete System-on-Chip (SoC) solutions for both mobile and network based communication systems, including new compression algorithms based on Burrows-Wheeler transform (BWT). The most complex task of the BWT algorithm is its lexicographic sorting of n cyclic rotations or a given string of n characters. The paper discusses the feasibility and VLSI implementation of this scalable BWT architecture in simulating and prototyping its systolic highly utilized hardware structure with Virtex FPGAs