Design and simulation of an efficient hardware architecture for still image compression applications

Includes bibliographical references (pages [109])Data compression is a technique that reduces the space required to represent a source data without degrading its quality. It is used extensively in applications such as image processing where the amount of information requires a lot of space to be stored. Many complex algorithms are available today that can achieve a high compression rate. The complexity of these algorithms makes the hardware implementation very difficult and costly. In this project, we analyzed the standard image compression algorithm, JPEG, in detail and determined the areas that make hardware design difficult. The proposed new algorithm can overcome the hardware design difficulties of the JPEG algorithm. The new algorithm uses Walsh-Hadamard (WH) transform to convert the pixel data into frequency domain. A new shifting quantization technique has been used to quantize the data. The hardware design of the new algorithm has been developed using ?Verilog Hardware Description Language.? The design was mapped and simulated in a XILINX 4052XL FPGA (field programmable gate arrays). The results show that an image encoder can be designed with less than 50,000 gates and, at the same time, give about 80% of the compression that the JPEG algorithm provides.M.S. (Master of Science