Meta VHDL for higher level controller modeling and synthesis

Presents Meta VHDL (MV) a hardware description language based on VHDL with the addition of primitives to support an efficient specification of hierarchical and communicating finite state machines. MV supplements VHDL with three new paradigms: hierarchical composition of FSMs, exception handlers and global transitions between FSMs. An algorithm that translates MV specifications into VHDL models is also presented. First experiments show that the use of these new paradigms for the specification of high level controllers allows for a fourfold reduction of the description size when compared to the VHDL model