An approach to Verilog-VHDL interoperability for synchronous designs

ISBN: 0412813300This paper suggests that synchronous designs written in either Verilog or VHDL can be interpreted in terms of a common hierarchical finite state machine model, and shows the principles for extracting the semantics of designs described in either language. Sublanguages with identical semantics are identified, and an algorithm for inferring a minimal number of state variables from VHDL processes is given. This common semantic model can be used as a kernel for cycle-based simulation, formal verification, and synthesis, irrespective of the source language. In particular, Verilog and VHDL descriptions can be proven equivalent, and modules developed in one language can be reused in projects documented in the other one. This approach has been prototyped by the implementation of a semantic link between the VIS system of Berkeley and the Prevail system of TIMA