Add to ORKGISBN 0818619716Special-purpose chips based on highly parallel architectures, for possible use in videophone, videoconference, digital TV distribution and HDTV codecs, are considered. Functional interface specifications for a motion estimator to be inserted in a coder system are detailed. The range of possible operative part-kernel architectures is derived, based on formal high-level synthesis methods. A novel implementation using redundant base 2 digital-serial arithmetic is presented, resulting in a compact (70000 transistors) motion estimation VLSI block
This paper proposes a hardware friendly multi-resolution motion estimation algorithm and VLSI archit...
In this paper, we propose a new parallel hardware architecture for the mode decision algorithm, that...
This work had pursued the compilation and organization of some ideas about motion determining from i...
The need of video compression in the modern age of visual communication cannot be over-emphasized. T...
In this paper an architecture is described that implements motion estimation in image coding, using ...
this paper a parametrizable architecture of a motion estimator is presented. The architecture suppor...
This paper presents a VLSI architecture for a low complexity motion estimation algorithm, referred t...
[[abstract]]In this paper, we propose a hierarchical motion estimation algorithm and develop VLSI ar...
The video part of AVS has been finalized. In order to enhance coding performance, AVS video standard...
With the advent of new video standards such as MPEG-4 part-10 and H.264/H.26L, demands for advanced ...
In the new video compression standards, AVC and AVS, the motion estimation adopts many new features ...
This paper describes a new parallel architecture dedicated to multi-motion estimation. The input ima...
In this paper, the VLSI hardware complexity for H.264 integer motion estimation is analyzed, several...
This paper presents an efficient VLSI architecture design to achieve real time video processing usin...
High throughput, heavy bandwidth requirement, huge on-chip memory consumption, and complex data flow...
This paper proposes a hardware friendly multi-resolution motion estimation algorithm and VLSI archit...
In this paper, we propose a new parallel hardware architecture for the mode decision algorithm, that...
This work had pursued the compilation and organization of some ideas about motion determining from i...
The need of video compression in the modern age of visual communication cannot be over-emphasized. T...
In this paper an architecture is described that implements motion estimation in image coding, using ...
this paper a parametrizable architecture of a motion estimator is presented. The architecture suppor...
This paper presents a VLSI architecture for a low complexity motion estimation algorithm, referred t...
[[abstract]]In this paper, we propose a hierarchical motion estimation algorithm and develop VLSI ar...
The video part of AVS has been finalized. In order to enhance coding performance, AVS video standard...
With the advent of new video standards such as MPEG-4 part-10 and H.264/H.26L, demands for advanced ...
In the new video compression standards, AVC and AVS, the motion estimation adopts many new features ...
This paper describes a new parallel architecture dedicated to multi-motion estimation. The input ima...
In this paper, the VLSI hardware complexity for H.264 integer motion estimation is analyzed, several...
This paper presents an efficient VLSI architecture design to achieve real time video processing usin...
High throughput, heavy bandwidth requirement, huge on-chip memory consumption, and complex data flow...
This paper proposes a hardware friendly multi-resolution motion estimation algorithm and VLSI archit...
In this paper, we propose a new parallel hardware architecture for the mode decision algorithm, that...
This work had pursued the compilation and organization of some ideas about motion determining from i...