Compiler-driven cache management using a state level transition model

Cache performance is critical in cache-based supercomputers, where the cache-miss/cache-hit memory reference delay ratio is typically large. Using compile-time analysis, program behavior can be predicted, and cache control directives can be embedded in the generated code. Thus, cache performance can be improved in a way not possible using conventional techniques. Given hardware able to selectively bypass the cache, cache performance can be increased because pollution can be minimized. Cache line replacement can also be controlled by the compiler (rather than by LRU, etc.), further enhancing performance. The research consists of the development of a model and algorithms providing optimal, or near optimal, cache performance by compiler management of cache