Compile Time Techniques for Using the Priority Data Cache to Reduce Memory Access Delays

The potential of high-performance systems, especially parallel machines, is generally limited by the bandwidth between processors and memory. To achieve the performance of which these machines should be capable, global memory access delays must be alleviated. One approach is to better utilize local storage. To this end, we previously proposed a new local storage facility, the priority data cache (PDC), that supports integrated hardware-software control. This paper focuses on developing a compile-time methodology for using the PDC. We detail the basic algorithm and propose enhancements based on initial performance results. Key words: data access optimization, data prioritization, compiler-directed cache management, memory hierarchies, data reuse, data locality, dependence analysis, program optimization. Much of this work was completed while Elana D. Granston was at the Center for Supercomputing Research and Development. y Support was provided by the Department of Energy under Grant..