Leakage grading of inputs to CMOS logic

Supply voltages and threshold voltages continue to be aggressively scaled down in order to obtain power reduction, performance improvement, and increasing integration density. This leads to leakage current becoming a much more significant component of power than it has been in the past. We have previously shown that substantial leakage reduction can be achieved in single Vt circuits by turning off stitcks of transistors. A theoretical model was also derived which predicts the quiescent leakage current and the idle time required to reach quiescent levels. In this report, we will review the leakage estimation model, outline a method for evaluating the leakage assocated with an input vector, and use the model to identify inputs which minimize leakage in a variety of test cases