Leakage Current Mechanisms and Leakage Reduction Techniques in Deep-Submicrometer CMOS Circuits

High leakage current in deep-submicrometer regimes is be-coming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thick-ness are reduced. Consequently, the identification and modeling of different leakage components is very important for estimation and reduction of leakage power, especially for low-power appli-cations. This paper reviews various transistor intrinsic leakage mechanisms, including weak inversion, drain-induced barrier lowering, gate-induced drain leakage, and gate oxide tunneling. Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices. Finally, the paper explores different circuit techniques to reduce the leakage power consumption. Keywords—Channel engineering, CMOS, dynamic V dd, dy-namic V th, gate leakage, leakage current, low-leakage memory, multiple V dd, multiple V th, scaling, stacking effect, subthreshold current, tunneling. I